rdmsr 83 arch/x86/kernel/acpi/sleep.c rdmsr(MSR_EFER, header->pmode_efer_low,
rdmsr 829 arch/x86/kernel/apic_32.c rdmsr(MSR_IA32_APICBASE, l, h);
rdmsr 1221 arch/x86/kernel/apic_32.c rdmsr(MSR_IA32_APICBASE, l, h);
rdmsr 1244 arch/x86/kernel/apic_32.c rdmsr(MSR_IA32_APICBASE, l, h);
rdmsr 1655 arch/x86/kernel/apic_32.c rdmsr(MSR_IA32_APICBASE, l, h);
rdmsr 714 arch/x86/kernel/apic_64.c rdmsr(MSR_IA32_APICBASE, l, h);
rdmsr 1043 arch/x86/kernel/apic_64.c rdmsr(MSR_IA32_APICBASE, msr, msr2);
rdmsr 1056 arch/x86/kernel/apic_64.c rdmsr(MSR_IA32_APICBASE, msr, msr2);
rdmsr 1598 arch/x86/kernel/apic_64.c rdmsr(MSR_IA32_APICBASE, l, h);
rdmsr 103 arch/x86/kernel/cpu/amd.c rdmsr(MSR_K6_WHCR, l, h);
rdmsr 124 arch/x86/kernel/cpu/amd.c rdmsr(MSR_K6_WHCR, l, h);
rdmsr 158 arch/x86/kernel/cpu/amd.c rdmsr(MSR_K7_HWCR, l, h);
rdmsr 171 arch/x86/kernel/cpu/amd.c rdmsr(MSR_K7_CLK_CTL, l, h);
rdmsr 204 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
rdmsr 225 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
rdmsr 236 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
rdmsr 260 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_VIA_FCR, lo, hi);
rdmsr 268 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_VIA_RNG, lo, hi);
rdmsr 282 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_VIA_FCR, lo, hi);
rdmsr 383 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
rdmsr 403 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
rdmsr 419 arch/x86/kernel/cpu/centaur.c rdmsr(MSR_IDT_FCR1, lo, hi);
rdmsr 161 arch/x86/kernel/cpu/common.c rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
rdmsr 158 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c rdmsr(cmd->addr.msr.reg, cmd->val, h);
rdmsr 176 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c rdmsr(cmd->addr.msr.reg, lo, hi);
rdmsr 282 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c rdmsr(MSR_IA32_APERF, aperf_cur.split.lo, aperf_cur.split.hi);
rdmsr 283 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c rdmsr(MSR_IA32_MPERF, mperf_cur.split.lo, mperf_cur.split.hi);
rdmsr 48 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
rdmsr 67 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
rdmsr 71 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
rdmsr 84 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
rdmsr 94 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
rdmsr 102 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
rdmsr 176 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(0x1153, lo, hi);
rdmsr 181 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(0x1154, lo, hi);
rdmsr 219 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
rdmsr 311 arch/x86/kernel/cpu/cpufreq/e_powersaver.c rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
rdmsr 127 arch/x86/kernel/cpu/cpufreq/longhaul.c rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
rdmsr 866 arch/x86/kernel/cpu/cpufreq/longhaul.c rdmsr(MSR_VIA_LONGHAUL, lo, hi);
rdmsr 42 arch/x86/kernel/cpu/cpufreq/longrun.c rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
rdmsr 49 arch/x86/kernel/cpu/cpufreq/longrun.c rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
rdmsr 98 arch/x86/kernel/cpu/cpufreq/longrun.c rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
rdmsr 110 arch/x86/kernel/cpu/cpufreq/longrun.c rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
rdmsr 189 arch/x86/kernel/cpu/cpufreq/longrun.c rdmsr(MSR_TMTA_LRTI_READOUT, msr_lo, msr_hi);
rdmsr 191 arch/x86/kernel/cpu/cpufreq/longrun.c rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
rdmsr 196 arch/x86/kernel/cpu/cpufreq/longrun.c rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi);
rdmsr 212 arch/x86/kernel/cpu/cpufreq/longrun.c rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
rdmsr 105 arch/x86/kernel/cpu/cpufreq/powernow-k8.c rdmsr(MSR_FIDVID_STATUS, lo, hi);
rdmsr 119 arch/x86/kernel/cpu/cpufreq/powernow-k8.c rdmsr(MSR_PSTATE_STATUS, lo, hi);
rdmsr 129 arch/x86/kernel/cpu/cpufreq/powernow-k8.c rdmsr(MSR_FIDVID_STATUS, lo, hi);
rdmsr 158 arch/x86/kernel/cpu/cpufreq/powernow-k8.c rdmsr(MSR_FIDVID_STATUS, lo, hi);
rdmsr 314 arch/x86/kernel/cpu/cpufreq/powernow-k8.c rdmsr(MSR_FIDVID_STATUS, lo, maxvid);
rdmsr 821 arch/x86/kernel/cpu/cpufreq/powernow-k8.c rdmsr(MSR_PSTATE_CUR_LIMIT, hi, lo);
rdmsr 834 arch/x86/kernel/cpu/cpufreq/powernow-k8.c rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi);
rdmsr 333 arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c rdmsr(MSR_IA32_PERF_STATUS, l, h);
rdmsr 343 arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c rdmsr(MSR_IA32_PERF_CTL, l, h);
rdmsr 391 arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c rdmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr 399 arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c rdmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr 537 arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
rdmsr 74 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
rdmsr 110 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
rdmsr 130 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
rdmsr 146 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
rdmsr 162 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c rdmsr(0x2c, msr_lo, msr_hi);
rdmsr 313 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
rdmsr 325 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
rdmsr 115 arch/x86/kernel/cpu/intel.c rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
rdmsr 217 arch/x86/kernel/cpu/intel.c rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
rdmsr 224 arch/x86/kernel/cpu/intel.c rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
rdmsr 257 arch/x86/kernel/cpu/intel.c rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
rdmsr 26 arch/x86/kernel/cpu/mcheck/k7.c rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
rdmsr 34 arch/x86/kernel/cpu/mcheck/k7.c rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
rdmsr 45 arch/x86/kernel/cpu/mcheck/k7.c rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
rdmsr 49 arch/x86/kernel/cpu/mcheck/k7.c rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
rdmsr 85 arch/x86/kernel/cpu/mcheck/k7.c rdmsr(MSR_IA32_MCG_CAP, l, h);
rdmsr 92 arch/x86/kernel/cpu/mcheck/mce_amd_64.c rdmsr(b->address, mci_misc_lo, mci_misc_hi);
rdmsr 321 arch/x86/kernel/cpu/mcheck/mce_amd_64.c rdmsr(b->address, low, high);
rdmsr 49 arch/x86/kernel/cpu/mcheck/mce_intel_64.c rdmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr 71 arch/x86/kernel/cpu/mcheck/mce_intel_64.c rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
rdmsr 74 arch/x86/kernel/cpu/mcheck/mce_intel_64.c rdmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr 35 arch/x86/kernel/cpu/mcheck/non-fatal.c rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
rdmsr 86 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr 107 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
rdmsr 113 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MISC_ENABLE, l, h);
rdmsr 132 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
rdmsr 133 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
rdmsr 134 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
rdmsr 135 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
rdmsr 136 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
rdmsr 137 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
rdmsr 138 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
rdmsr 139 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
rdmsr 140 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
rdmsr 141 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
rdmsr 151 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
rdmsr 170 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
rdmsr 181 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
rdmsr 185 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
rdmsr 207 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(msr, low, high);
rdmsr 230 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_CAP, l, h);
rdmsr 245 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MCG_CAP, l, h);
rdmsr 22 arch/x86/kernel/cpu/mcheck/p5.c rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
rdmsr 23 arch/x86/kernel/cpu/mcheck/p5.c rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
rdmsr 46 arch/x86/kernel/cpu/mcheck/p5.c rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
rdmsr 47 arch/x86/kernel/cpu/mcheck/p5.c rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
rdmsr 26 arch/x86/kernel/cpu/mcheck/p6.c rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
rdmsr 34 arch/x86/kernel/cpu/mcheck/p6.c rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
rdmsr 45 arch/x86/kernel/cpu/mcheck/p6.c rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
rdmsr 49 arch/x86/kernel/cpu/mcheck/p6.c rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
rdmsr 71 arch/x86/kernel/cpu/mcheck/p6.c rdmsr(msr, low, high);
rdmsr 103 arch/x86/kernel/cpu/mcheck/p6.c rdmsr(MSR_IA32_MCG_CAP, l, h);
rdmsr 30 arch/x86/kernel/cpu/mcheck/winchip.c rdmsr(MSR_IDT_FCR1, lo, hi);
rdmsr 14 arch/x86/kernel/cpu/mtrr/amd.c rdmsr(MSR_K6_UWCCR, low, high);
rdmsr 64 arch/x86/kernel/cpu/mtrr/amd.c rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
rdmsr 108 arch/x86/kernel/cpu/mtrr/centaur.c rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
rdmsr 157 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
rdmsr 158 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
rdmsr 181 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRfix64K_00000_MSR, p[0], p[1]);
rdmsr 184 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRfix16K_80000_MSR + i, p[2 + i * 2], p[3 + i * 2]);
rdmsr 186 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRfix4K_C0000_MSR + i, p[6 + i * 2], p[7 + i * 2]);
rdmsr 217 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRcap_MSR, lo, dummy);
rdmsr 225 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRdefType_MSR, lo, dummy);
rdmsr 232 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MSR_K8_TOP_MEM2, low, high);
rdmsr 322 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MSR_K8_SYSCFG, lo, hi);
rdmsr 341 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(msr, lo, hi);
rdmsr 384 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
rdmsr 393 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
rdmsr 441 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRphysBase_MSR(index), lo, hi);
rdmsr 449 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRphysMask_MSR(index), lo, hi);
rdmsr 527 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
rdmsr 651 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRcap_MSR, config, dummy);
rdmsr 107 arch/x86/kernel/cpu/mtrr/main.c rdmsr(MTRRcap_MSR, config, dummy);
rdmsr 1229 arch/x86/kernel/cpu/mtrr/main.c rdmsr(MTRRdefType_MSR, def, dummy);
rdmsr 1576 arch/x86/kernel/cpu/mtrr/main.c rdmsr(MTRRdefType_MSR, def, dummy);
rdmsr 38 arch/x86/kernel/cpu/mtrr/state.c rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
rdmsr 481 arch/x86/kernel/cpu/perfctr-watchdog.c rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
rdmsr 524 arch/x86/kernel/cpu/perfctr-watchdog.c rdmsr(p4_controls[i], low, high);
rdmsr 84 arch/x86/kernel/cpu/transmeta.c rdmsr(0x80860004, cap_mask, uk);
rdmsr 36 arch/x86/kernel/geode_32.c rdmsr(lbars[i].msr, lo, hi);
rdmsr 121 arch/x86/kernel/geode_32.c rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
rdmsr 150 arch/x86/kernel/mfgpt_32.c rdmsr(msr, value, dummy);
rdmsr 178 arch/x86/kernel/mfgpt_32.c rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
rdmsr 192 arch/x86/kernel/mfgpt_32.c rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
rdmsr 173 arch/x86/kernel/microcode_intel.c rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
rdmsr 181 arch/x86/kernel/microcode_intel.c rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
rdmsr 340 arch/x86/kernel/microcode_intel.c rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
rdmsr 270 arch/x86/kernel/process.c rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
rdmsr 566 arch/x86/kernel/vmi_32.c rdmsr(MSR_EFER, l, h);
rdmsr 1085 arch/x86/kvm/vmx.c rdmsr(msr, vmx_msr_low, vmx_msr_high);
rdmsr 1158 arch/x86/kvm/vmx.c rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
rdmsr 1176 arch/x86/kvm/vmx.c rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
rdmsr 1970 arch/x86/kvm/vmx.c rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
rdmsr 16 arch/x86/lib/msr-on-cpu.c rdmsr(rv->msr_no, rv->l, rv->h);
rdmsr 604 arch/x86/mm/init_32.c rdmsr(MSR_EFER, l, h);
rdmsr 138 arch/x86/oprofile/nmi_int.c rdmsr(counters[i].addr,
rdmsr 146 arch/x86/oprofile/nmi_int.c rdmsr(controls[i].addr,
rdmsr 30 arch/x86/oprofile/op_model_amd.c #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
rdmsr 35 arch/x86/oprofile/op_model_amd.c #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
rdmsr 210 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
rdmsr 214 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
rdmsr 217 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high);
rdmsr 226 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
rdmsr 235 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSOPCTL, low, high);
rdmsr 237 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSOPRIP, low, high);
rdmsr 240 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSOPDATA, low, high);
rdmsr 243 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSOPDATA2, low, high);
rdmsr 246 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSOPDATA3, low, high);
rdmsr 249 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSDCLINAD, low, high);
rdmsr 252 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high);
rdmsr 260 arch/x86/oprofile/op_model_amd.c rdmsr(MSR_AMD64_IBSOPCTL, low, high);
rdmsr 353 arch/x86/oprofile/op_model_p4.c #define ESCR_READ(escr, high, ev, i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
rdmsr 364 arch/x86/oprofile/op_model_p4.c #define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
rdmsr 371 arch/x86/oprofile/op_model_p4.c #define CTR_READ(l, h, i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h)); } while (0)
rdmsr 559 arch/x86/oprofile/op_model_p4.c rdmsr(MSR_IA32_MISC_ENABLE, low, high);
rdmsr 569 arch/x86/oprofile/op_model_p4.c rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
rdmsr 26 arch/x86/oprofile/op_model_ppro.c #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
rdmsr 32 arch/x86/oprofile/op_model_ppro.c #define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
rdmsr 93 include/asm-x86/apic.h rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
rdmsr 225 include/asm-x86/msr.h rdmsr(msr_no, *l, *h);