L1_CACHE_BYTES    194 arch/x86/mm/numa_32.c 	size = ALIGN(size, L1_CACHE_BYTES);
L1_CACHE_BYTES     82 arch/x86/mm/numa_64.c 	nodemap_size = roundup(sizeof(s16) * memnodemapsize, L1_CACHE_BYTES);
L1_CACHE_BYTES     84 arch/x86/mm/numa_64.c 				      nodemap_size, L1_CACHE_BYTES);
L1_CACHE_BYTES   1108 fs/dcache.c    	hash += ((unsigned long) parent ^ GOLDEN_RATIO_PRIME) / L1_CACHE_BYTES;
L1_CACHE_BYTES    174 fs/file.c      				 2 * nr / BITS_PER_BYTE, L1_CACHE_BYTES));
L1_CACHE_BYTES    706 fs/inode.c     			L1_CACHE_BYTES;
L1_CACHE_BYTES     55 fs/namespace.c 	unsigned long tmp = ((unsigned long)mnt / L1_CACHE_BYTES);
L1_CACHE_BYTES     56 fs/namespace.c 	tmp += ((unsigned long)dentry / L1_CACHE_BYTES);
L1_CACHE_BYTES     20 include/asm-frv/cache.h #define __cacheline_aligned	__attribute__((aligned(L1_CACHE_BYTES)))
L1_CACHE_BYTES     21 include/asm-frv/cache.h #define ____cacheline_aligned	__attribute__((aligned(L1_CACHE_BYTES)))
L1_CACHE_BYTES     15 include/asm-generic/bitops/atomic.h #  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
L1_CACHE_BYTES     19 include/asm-mn10300/cache.h #define L1_CACHE_DISPARITY	(L1_CACHE_NENTRIES * L1_CACHE_BYTES)
L1_CACHE_BYTES     21 include/asm-mn10300/cache.h #define L1_CACHE_DISPARITY	L1_CACHE_NENTRIES * L1_CACHE_BYTES
L1_CACHE_BYTES     31 include/asm-mn10300/cache.h 		 (ENTRY) * L1_CACHE_BYTES, u32)
L1_CACHE_BYTES     34 include/asm-mn10300/cache.h 	__SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
L1_CACHE_BYTES     36 include/asm-mn10300/cache.h 	__SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
L1_CACHE_BYTES     38 include/asm-mn10300/cache.h 	__SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
L1_CACHE_BYTES     40 include/asm-mn10300/cache.h 	__SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
L1_CACHE_BYTES     28 include/asm-parisc/atomic.h #  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
L1_CACHE_BYTES     27 include/asm-parisc/cache.h #define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
L1_CACHE_BYTES     29 include/asm-parisc/cache.h #define SMP_CACHE_BYTES L1_CACHE_BYTES
L1_CACHE_BYTES    155 include/asm-x86/tlbflush.h 	char __cacheline_padding[L1_CACHE_BYTES-8];
L1_CACHE_BYTES     18 include/asm-xtensa/cache.h #define SMP_CACHE_BYTES	L1_CACHE_BYTES
L1_CACHE_BYTES    167 include/asm-xtensa/dma-mapping.h 	return L1_CACHE_BYTES;
L1_CACHE_BYTES      8 include/linux/cache.h #define L1_CACHE_ALIGN(x) ALIGN(x, L1_CACHE_BYTES)
L1_CACHE_BYTES     12 include/linux/cache.h #define SMP_CACHE_BYTES L1_CACHE_BYTES
L1_CACHE_BYTES     64 include/linux/cache.h #define cache_line_size()	L1_CACHE_BYTES
L1_CACHE_BYTES      5 include/linux/kmalloc_sizes.h #if L1_CACHE_BYTES < 64
L1_CACHE_BYTES      9 include/linux/kmalloc_sizes.h #if L1_CACHE_BYTES < 128
L1_CACHE_BYTES     50 include/linux/prefetch.h #define PREFETCH_STRIDE (4*L1_CACHE_BYTES)
L1_CACHE_BYTES    160 kernel/audit_tree.c 	unsigned long n = (unsigned long)inode / L1_CACHE_BYTES;
L1_CACHE_BYTES    169 kernel/fork.c  #define ARCH_MIN_TASKALIGN	L1_CACHE_BYTES
L1_CACHE_BYTES     10 mm/allocpercpu.c #define cache_line_size()	L1_CACHE_BYTES
L1_CACHE_BYTES   2269 mm/shmem.c     				L1_CACHE_BYTES), GFP_KERNEL);
L1_CACHE_BYTES    168 mm/slob.c      #define SLOB_ALIGN L1_CACHE_BYTES