wrmsr 831 arch/x86/kernel/apic_32.c wrmsr(MSR_IA32_APICBASE, l, h);
wrmsr 1227 arch/x86/kernel/apic_32.c wrmsr(MSR_IA32_APICBASE, l, h);
wrmsr 1658 arch/x86/kernel/apic_32.c wrmsr(MSR_IA32_APICBASE, l, h);
wrmsr 716 arch/x86/kernel/apic_64.c wrmsr(MSR_IA32_APICBASE, l, h);
wrmsr 1059 arch/x86/kernel/apic_64.c wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
wrmsr 1601 arch/x86/kernel/apic_64.c wrmsr(MSR_IA32_APICBASE, l, h);
wrmsr 109 arch/x86/kernel/cpu/amd.c wrmsr(MSR_K6_WHCR, l, h);
wrmsr 130 arch/x86/kernel/cpu/amd.c wrmsr(MSR_K6_WHCR, l, h);
wrmsr 160 arch/x86/kernel/cpu/amd.c wrmsr(MSR_K7_HWCR, l, h);
wrmsr 175 arch/x86/kernel/cpu/amd.c wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
wrmsr 36 arch/x86/kernel/cpu/centaur.c wrmsr(reg+MSR_IDT_MCR0, lo, hi);
wrmsr 181 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_MCR0+i, 0, 0);
wrmsr 207 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
wrmsr 214 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_MCR0+i, 0, 0);
wrmsr 229 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
wrmsr 238 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
wrmsr 262 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_VIA_FCR, lo, hi);
wrmsr 270 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_VIA_RNG, lo, hi);
wrmsr 284 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_VIA_FCR, lo, hi);
wrmsr 362 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
wrmsr 391 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
wrmsr 411 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
wrmsr 425 arch/x86/kernel/cpu/centaur.c wrmsr(MSR_IDT_FCR1, newlo, hi);
wrmsr 163 arch/x86/kernel/cpu/common.c wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
wrmsr 178 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c wrmsr(cmd->addr.msr.reg, lo, hi);
wrmsr 285 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c wrmsr(MSR_IA32_APERF, 0,0);
wrmsr 286 arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c wrmsr(MSR_IA32_MPERF, 0,0);
wrmsr 79 arch/x86/kernel/cpu/cpufreq/e_powersaver.c wrmsr(MSR_IA32_PERF_CTL, dest_state & 0xffff, 0);
wrmsr 107 arch/x86/kernel/cpu/cpufreq/longrun.c wrmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
wrmsr 115 arch/x86/kernel/cpu/cpufreq/longrun.c wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
wrmsr 190 arch/x86/kernel/cpu/cpufreq/longrun.c wrmsr(MSR_TMTA_LRTI_READOUT, msr_hi, msr_hi);
wrmsr 195 arch/x86/kernel/cpu/cpufreq/longrun.c wrmsr(MSR_TMTA_LRTI_READOUT, 0, msr_hi);
wrmsr 227 arch/x86/kernel/cpu/cpufreq/longrun.c wrmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi);
wrmsr 233 arch/x86/kernel/cpu/cpufreq/longrun.c wrmsr(MSR_TMTA_LONGRUN_CTRL, save_lo, save_hi);
wrmsr 54 arch/x86/kernel/cpu/cpufreq/powernow-k6.c wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
wrmsr 57 arch/x86/kernel/cpu/cpufreq/powernow-k6.c wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
wrmsr 91 arch/x86/kernel/cpu/cpufreq/powernow-k6.c wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
wrmsr 97 arch/x86/kernel/cpu/cpufreq/powernow-k6.c wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
wrmsr 164 arch/x86/kernel/cpu/cpufreq/powernow-k8.c wrmsr(MSR_FIDVID_CTL, lo, hi);
wrmsr 185 arch/x86/kernel/cpu/cpufreq/powernow-k8.c wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION);
wrmsr 227 arch/x86/kernel/cpu/cpufreq/powernow-k8.c wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS);
wrmsr 270 arch/x86/kernel/cpu/cpufreq/powernow-k8.c wrmsr(MSR_PSTATE_CTRL, pstate, 0);
wrmsr 396 arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c wrmsr(MSR_IA32_MISC_ENABLE, l, h);
wrmsr 564 arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
wrmsr 591 arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
wrmsr 120 arch/x86/kernel/cpu/intel.c wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
wrmsr 55 arch/x86/kernel/cpu/mcheck/k7.c wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
wrmsr 68 arch/x86/kernel/cpu/mcheck/k7.c wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
wrmsr 87 arch/x86/kernel/cpu/mcheck/k7.c wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
wrmsr 93 arch/x86/kernel/cpu/mcheck/k7.c wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
wrmsr 98 arch/x86/kernel/cpu/mcheck/k7.c wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
wrmsr 99 arch/x86/kernel/cpu/mcheck/k7.c wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
wrmsr 464 arch/x86/kernel/cpu/mcheck/mce_64.c wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
wrmsr 113 arch/x86/kernel/cpu/mcheck/mce_amd_64.c wrmsr(b->address, mci_misc_lo, mci_misc_hi);
wrmsr 162 arch/x86/kernel/cpu/mcheck/mce_amd_64.c wrmsr(address, low, high);
wrmsr 72 arch/x86/kernel/cpu/mcheck/mce_intel_64.c wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
wrmsr 75 arch/x86/kernel/cpu/mcheck/mce_intel_64.c wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
wrmsr 48 arch/x86/kernel/cpu/mcheck/non-fatal.c wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
wrmsr 108 arch/x86/kernel/cpu/mcheck/p4.c wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
wrmsr 114 arch/x86/kernel/cpu/mcheck/p4.c wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
wrmsr 210 arch/x86/kernel/cpu/mcheck/p4.c wrmsr(msr, 0UL, 0UL);
wrmsr 217 arch/x86/kernel/cpu/mcheck/p4.c wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
wrmsr 232 arch/x86/kernel/cpu/mcheck/p4.c wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
wrmsr 236 arch/x86/kernel/cpu/mcheck/p4.c wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
wrmsr 237 arch/x86/kernel/cpu/mcheck/p4.c wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
wrmsr 74 arch/x86/kernel/cpu/mcheck/p6.c wrmsr(msr, 0UL, 0UL);
wrmsr 81 arch/x86/kernel/cpu/mcheck/p6.c wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
wrmsr 105 arch/x86/kernel/cpu/mcheck/p6.c wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
wrmsr 114 arch/x86/kernel/cpu/mcheck/p6.c wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
wrmsr 117 arch/x86/kernel/cpu/mcheck/p6.c wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
wrmsr 33 arch/x86/kernel/cpu/mcheck/winchip.c wrmsr(MSR_IDT_FCR1, lo, hi);
wrmsr 86 arch/x86/kernel/cpu/mtrr/amd.c wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
wrmsr 88 arch/x86/kernel/cpu/mtrr/centaur.c wrmsr(MSR_IDT_MCR0 + reg, low, high);
wrmsr 112 arch/x86/kernel/cpu/mtrr/centaur.c wrmsr(MSR_IDT_MCR_CTRL, lo, hi); /* unlock MCR */
wrmsr 124 arch/x86/kernel/cpu/mtrr/centaur.c wrmsr(MSR_IDT_MCR0 + i, 0, 0);
wrmsr 140 arch/x86/kernel/cpu/mtrr/centaur.c wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
wrmsr 164 arch/x86/kernel/cpu/mtrr/centaur.c wrmsr(MSR_IDT_MCR0 + i, 0, 0);
wrmsr 167 arch/x86/kernel/cpu/mtrr/centaur.c wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0); /* Write only */
wrmsr 265 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(perfctr_msr, (u32)(-count), 0);
wrmsr 296 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(evntsel_msr, evntsel, 0);
wrmsr 309 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(evntsel_msr, evntsel, 0);
wrmsr 318 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(wd->evntsel_msr, 0, 0);
wrmsr 385 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(evntsel_msr, evntsel, 0);
wrmsr 399 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(evntsel_msr, evntsel, 0);
wrmsr 526 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(p4_controls[i], low, high);
wrmsr 552 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(evntsel_msr, evntsel, 0);
wrmsr 553 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(cccr_msr, cccr_val, 0);
wrmsr 565 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(cccr_msr, cccr_val, 0);
wrmsr 572 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(wd->cccr_msr, 0, 0);
wrmsr 573 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(wd->evntsel_msr, 0, 0);
wrmsr 678 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(evntsel_msr, evntsel, 0);
wrmsr 691 arch/x86/kernel/cpu/perfctr-watchdog.c wrmsr(evntsel_msr, evntsel, 0);
wrmsr 85 arch/x86/kernel/cpu/transmeta.c wrmsr(0x80860004, ~0, uk);
wrmsr 87 arch/x86/kernel/cpu/transmeta.c wrmsr(0x80860004, cap_mask, uk);
wrmsr 259 arch/x86/kernel/ds.c wrmsr(MSR_IA32_DS_AREA, (unsigned long)context->ds, 0);
wrmsr 126 arch/x86/kernel/geode_32.c wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
wrmsr 68 arch/x86/kernel/mfgpt_32.c wrmsr(MSR_MFGPT_SETUP, val, dummy);
wrmsr 157 arch/x86/kernel/mfgpt_32.c wrmsr(msr, value, dummy);
wrmsr 201 arch/x86/kernel/mfgpt_32.c wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
wrmsr 177 arch/x86/kernel/microcode_intel.c wrmsr(MSR_IA32_UCODE_REV, 0, 0);
wrmsr 331 arch/x86/kernel/microcode_intel.c wrmsr(MSR_IA32_UCODE_WRITE,
wrmsr 334 arch/x86/kernel/microcode_intel.c wrmsr(MSR_IA32_UCODE_REV, 0, 0);
wrmsr 439 arch/x86/kernel/process_32.c wrmsr(MSR_IA32_DS_AREA, ds_next, 0);
wrmsr 249 arch/x86/kernel/vmi_32.c wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
wrmsr 23 arch/x86/lib/msr-on-cpu.c wrmsr(rv->msr_no, rv->l, rv->h);
wrmsr 606 arch/x86/mm/init_32.c wrmsr(MSR_EFER, l, h);
wrmsr 264 arch/x86/oprofile/nmi_int.c wrmsr(controls[i].addr,
wrmsr 272 arch/x86/oprofile/nmi_int.c wrmsr(counters[i].addr,
wrmsr 31 arch/x86/oprofile/op_model_amd.c #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
wrmsr 36 arch/x86/oprofile/op_model_amd.c #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
wrmsr 230 arch/x86/oprofile/op_model_amd.c wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
wrmsr 264 arch/x86/oprofile/op_model_amd.c wrmsr(MSR_AMD64_IBSOPCTL, low, high);
wrmsr 313 arch/x86/oprofile/op_model_amd.c wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
wrmsr 319 arch/x86/oprofile/op_model_amd.c wrmsr(MSR_AMD64_IBSOPCTL, low, high);
wrmsr 344 arch/x86/oprofile/op_model_amd.c wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
wrmsr 350 arch/x86/oprofile/op_model_amd.c wrmsr(MSR_AMD64_IBSOPCTL, low, high);
wrmsr 354 arch/x86/oprofile/op_model_p4.c #define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
wrmsr 365 arch/x86/oprofile/op_model_p4.c #define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
wrmsr 372 arch/x86/oprofile/op_model_p4.c #define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1); } while (0)
wrmsr 572 arch/x86/oprofile/op_model_p4.c wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
wrmsr 579 arch/x86/oprofile/op_model_p4.c wrmsr(msrs->controls[i].addr, 0, 0);
wrmsr 28 arch/x86/oprofile/op_model_ppro.c do {wrmsr(msrs->counters[(c)].addr, -(u32)(l), 0); } while (0)
wrmsr 33 arch/x86/oprofile/op_model_ppro.c #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
wrmsr 238 arch/x86/vdso/vdso32-setup.c wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0);
wrmsr 239 arch/x86/vdso/vdso32-setup.c wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0);
wrmsr 240 arch/x86/vdso/vdso32-setup.c wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0);
wrmsr 83 include/asm-x86/apic.h wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
wrmsr 213 include/asm-x86/msr.h #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2))
wrmsr 215 include/asm-x86/msr.h #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
wrmsr 230 include/asm-x86/msr.h wrmsr(msr_no, l, h);
wrmsr 757 include/asm-x86/paravirt.h #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
wrmsr 526 include/asm-x86/processor.h wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);