CM_REG_INT_HLDCLR  903 sound/pci/cmipci.c 		snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
CM_REG_INT_HLDCLR  912 sound/pci/cmipci.c 		snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
CM_REG_INT_HLDCLR 1451 sound/pci/cmipci.c 	snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
CM_REG_INT_HLDCLR 1452 sound/pci/cmipci.c 	snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
CM_REG_INT_HLDCLR 2818 sound/pci/cmipci.c 	detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
CM_REG_INT_HLDCLR 2930 sound/pci/cmipci.c 		snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
CM_REG_INT_HLDCLR 3094 sound/pci/cmipci.c 	snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);	/* disable ints */
CM_REG_INT_HLDCLR 3128 sound/pci/cmipci.c 		switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
CM_REG_INT_HLDCLR 3325 sound/pci/cmipci.c 	CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
CM_REG_INT_HLDCLR 3358 sound/pci/cmipci.c 	snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
CM_REG_INT_HLDCLR 3383 sound/pci/cmipci.c 	snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);