azx_readl         678 sound/pci/hda/hda_intel.c 			return azx_readl(chip, IR);
azx_readl         738 sound/pci/hda/hda_intel.c 	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
azx_readl         766 sound/pci/hda/hda_intel.c 	azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
azx_readl         786 sound/pci/hda/hda_intel.c 	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
azx_readl         806 sound/pci/hda/hda_intel.c 	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
azx_readl         962 sound/pci/hda/hda_intel.c 	status = azx_readl(chip, INTSTS);
azx_readl        1171 sound/pci/hda/hda_intel.c 		if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
azx_readl        1481 sound/pci/hda/hda_intel.c 		azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
azx_readl        1532 sound/pci/hda/hda_intel.c 		azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);