MSR_IA32_APICBASE_ENABLE  830 arch/x86/kernel/apic_32.c 		l &= ~MSR_IA32_APICBASE_ENABLE;
MSR_IA32_APICBASE_ENABLE 1222 arch/x86/kernel/apic_32.c 		if (!(l & MSR_IA32_APICBASE_ENABLE)) {
MSR_IA32_APICBASE_ENABLE 1226 arch/x86/kernel/apic_32.c 			l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
MSR_IA32_APICBASE_ENABLE 1245 arch/x86/kernel/apic_32.c 	if (l & MSR_IA32_APICBASE_ENABLE)
MSR_IA32_APICBASE_ENABLE 1657 arch/x86/kernel/apic_32.c 		l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
MSR_IA32_APICBASE_ENABLE  715 arch/x86/kernel/apic_64.c 		l &= ~MSR_IA32_APICBASE_ENABLE;
MSR_IA32_APICBASE_ENABLE 1600 arch/x86/kernel/apic_64.c 		l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
MSR_IA32_APICBASE_ENABLE   92 arch/x86/kvm/lapic.c 	return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
MSR_IA32_APICBASE_ENABLE  665 arch/x86/kvm/svm.c 	svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
MSR_IA32_APICBASE_ENABLE 2032 arch/x86/kvm/vmx.c 	msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;