LVL_1_INST         37 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x06, LVL_1_INST, 8 },	/* 4-way set assoc, 32 byte line size */
LVL_1_INST         38 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x08, LVL_1_INST, 16 },	/* 4-way set assoc, 32 byte line size */
LVL_1_INST         46 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x30, LVL_1_INST, 32 },	/* 8-way set assoc, 64 byte line size */
LVL_1_INST        411 arch/x86/kernel/cpu/intel_cacheinfo.c 						case LVL_1_INST: