LVL_1_DATA         39 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x0a, LVL_1_DATA, 8 },	/* 2 way set assoc, 32 byte line size */
LVL_1_DATA         40 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x0c, LVL_1_DATA, 16 },	/* 4-way set assoc, 32 byte line size */
LVL_1_DATA         45 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x2c, LVL_1_DATA, 32 },	/* 8-way set assoc, 64 byte line size */
LVL_1_DATA         67 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x60, LVL_1_DATA, 16 },	/* 8-way set assoc, sectored cache, 64 byte line size */
LVL_1_DATA         68 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x66, LVL_1_DATA, 8 },	/* 4-way set assoc, sectored cache, 64 byte line size */
LVL_1_DATA         69 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x67, LVL_1_DATA, 16 },	/* 4-way set assoc, sectored cache, 64 byte line size */
LVL_1_DATA         70 arch/x86/kernel/cpu/intel_cacheinfo.c 	{ 0x68, LVL_1_DATA, 32 },	/* 4-way set assoc, sectored cache, 64 byte line size */
LVL_1_DATA        414 arch/x86/kernel/cpu/intel_cacheinfo.c 						case LVL_1_DATA: