XCHAL_DCACHE_LINEWIDTH   16 include/asm-xtensa/cache.h #define L1_CACHE_SHIFT	XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH   22 include/asm-xtensa/cache.h #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
XCHAL_DCACHE_LINEWIDTH   76 include/asm-xtensa/cacheasm.h 	__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH   93 include/asm-xtensa/cacheasm.h 	__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  100 include/asm-xtensa/cacheasm.h 	__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  108 include/asm-xtensa/cacheasm.h 			 XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  124 include/asm-xtensa/cacheasm.h 	__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  131 include/asm-xtensa/cacheasm.h 	__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  138 include/asm-xtensa/cacheasm.h 	__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  153 include/asm-xtensa/cacheasm.h 	__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  160 include/asm-xtensa/cacheasm.h 	__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  167 include/asm-xtensa/cacheasm.h 	__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH