MSR_P4_TBPU_ESCR0  331 arch/x86/oprofile/op_model_p4.c 		{ { CTR_MS_0, MSR_P4_TBPU_ESCR0},
MSR_P4_TBPU_ESCR0  337 arch/x86/oprofile/op_model_p4.c 		{ { CTR_MS_0, MSR_P4_TBPU_ESCR0},