MSR_IA32_MC0_MISC 45 arch/x86/kernel/cpu/mcheck/k7.c rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh); MSR_IA32_MC0_MISC 241 arch/x86/kernel/cpu/mcheck/mce_64.c rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); MSR_IA32_MC0_MISC 127 arch/x86/kernel/cpu/mcheck/mce_amd_64.c address = MSR_IA32_MC0_MISC + bank * 4; MSR_IA32_MC0_MISC 199 arch/x86/kernel/cpu/mcheck/mce_amd_64.c address = MSR_IA32_MC0_MISC + bank * 4; MSR_IA32_MC0_MISC 524 arch/x86/kernel/cpu/mcheck/mce_amd_64.c MSR_IA32_MC0_MISC + bank * 4); MSR_IA32_MC0_MISC 181 arch/x86/kernel/cpu/mcheck/p4.c rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh); MSR_IA32_MC0_MISC 45 arch/x86/kernel/cpu/mcheck/p6.c rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh); MSR_IA32_MC0_MISC 750 arch/x86/kvm/x86.c case MSR_IA32_MC0_MISC: MSR_IA32_MC0_MISC 751 arch/x86/kvm/x86.c case MSR_IA32_MC0_MISC+4: MSR_IA32_MC0_MISC 752 arch/x86/kvm/x86.c case MSR_IA32_MC0_MISC+8: MSR_IA32_MC0_MISC 753 arch/x86/kvm/x86.c case MSR_IA32_MC0_MISC+12: MSR_IA32_MC0_MISC 754 arch/x86/kvm/x86.c case MSR_IA32_MC0_MISC+16: