REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi  391 include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi  307 include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112