REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask  244 include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask  196 include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56