REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask  230 include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask  182 include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48