regk_iop_sw_spu_rw_gio_clr_mask_default  684 include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h #define regk_iop_sw_spu_rw_gio_clr_mask_default   0x00000000
regk_iop_sw_spu_rw_gio_clr_mask_default  544 include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
regk_iop_sw_spu_rw_gio_clr_mask_default  516 include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h #define regk_iop_sw_spu_rw_gio_clr_mask_default   0x00000000
regk_iop_sw_spu_rw_gio_clr_mask_default  433 include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,