reg_iop_sw_spu_rw_gio_clr_mask_offset  226 include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h #define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
reg_iop_sw_spu_rw_gio_clr_mask_offset  162 include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h #define reg_iop_sw_spu_rw_gio_clr_mask_offset 48