reg_iop_sw_spu_rw_gio_clr_mask_hi_offset  310 include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h #define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
reg_iop_sw_spu_rw_gio_clr_mask_hi_offset  218 include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h #define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88