reg_iop_sw_spu_rw_gio_clr_mask_hi  341 include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h } reg_iop_sw_spu_rw_gio_clr_mask_hi;
reg_iop_sw_spu_rw_gio_clr_mask_hi  257 include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h } reg_iop_sw_spu_rw_gio_clr_mask_hi;