reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit  462 include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit  370 include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5