reg_iop_sw_mpu_rw_gio_oe_clr_mask  250 include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h } reg_iop_sw_mpu_rw_gio_oe_clr_mask;
reg_iop_sw_mpu_rw_gio_oe_clr_mask  206 include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h } reg_iop_sw_mpu_rw_gio_oe_clr_mask;