reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 1706 include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19
reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 1027 include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5